Conventionally, as general-purpose memories used in information processors such as computers or mobile communications devices, volatile memories such as DRAMs or SRAMs are used. Unless a current is continuously supplied to the volatile memories, the volatile memories lose all information. Therefore, it is necessary to provide non-volatile memories for storing information in addition to the volatile memories, and as the non-volatile memories, flash EEPROMs, hard disk drives and the like are used. As information processing becomes faster, an increase in speed of the non-volatile memories is an important issue. Moreover, in terms of the development of information devices for so-called ubiquitous computing in recent years, the development of high-speed non-volatile memories as key devices for ubiquitous computing has been strongly desired.
As an effective technique for increasing the speed of the non-volatile memory, an MRAM (Magnetic Random Access Memory) is known. In the MRAM, each of storage cells arranged in a matrix form includes a magnetic device. A currently practical MRAM uses a giant magneto-resistive effect (GMR). The GMR is a phenomenon that in a laminate in which two ferromagnetic layers are stacked so that the directions of the easy magnetization axes of the magnetic layers are parallel to each other, when the magnetization direction of each ferromagnetic layer is parallel to the easy magnetization axis, the resistance is minimum, and when the magnetization direction of each magnetic layer is antiparallel to the easy magnetization axis, the resistance is maximum. In an actual GMR device, each of two ferromagnetic layers includes a pinned layer of which the magnetization direction is pinned, and a free layer (a magnetic sensitive layer) of which the magnetization direction can be changed by an external magnetic field which are stacked with a non-magnetic layer in between. Each storage cell stores information of either of the two states corresponding to binary information “0” and “1”, and detects a difference in resistance corresponding to information as a change in current or voltage so as to read information.
Moreover, in a magnetic device using a tunneling magneto-resistive effect (TMR), the MR ratio can be much larger than that in the GMR device. The TMR is a phenomenon that in a laminate including two ferromagnetic layers (a pinned layer of which the magnetization direction is pinned and a magnetic sensitive layer of which the magnetization direction is changeable, that is, a free layer) stacked with an extremely thin insulating layer in between, the value of a tunnel current flowing through the insulating layer changes according to a relative angle between the magnetization directions of the two ferromagnetic layers. In other words, in the case where the magnetization directions are parallel to each other, the tunnel current is maximum (the resistance of the device is minimum), and in the case where the magnetization directions are antiparallel to each other, the tunnel current is minimum (the resistance of the device is maximum). Thus, in a TMR-MRAM, writing of stored information is performed as in the case of the GMR-MRAM, and reading of information is performed by a method of detecting a difference between relative magnetization directions of the ferromagnetic layers (parallel or antiparallel) as a difference in an output current or cell resistance through flowing a current through the insulating layer in a perpendicular direction to a layer surface.
As a specific example of the TMR device, a laminate structure of CoFe/Al oxide/CoFe is known, and its MR ratio is 40% or more. Moreover, the TMR device has high resistance, so it is considered that the TMR device easily matches a semiconductor device such as a MOS field effect transistor (MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor). Such advantages allow the TMR-MRAM to achieve a high output more easily than the GMR-MRAM, so improvements in the storage capacity and the access speed of the TMR-MRAM are expected.
As the cell array structure, a structure in which a plurality of TMR devices are connected in parallel on data lines, and a semiconductor device for selection is arranged corresponding to each of the TMR devices or each of the data lines has been proposed. Moreover, a structure in which the TMR devices are arranged in a matrix form through the use of row data lines and column data lines, and a transistor for selection is arranged for each data line has been proposed.
Among them, a structure in which a semiconductor device is arranged for each TMR device has the best characteristic in power consumption efficiency at the time of reading. However, in the case where variations in the characteristics of the semiconductor devices occur, noises due to the variations are not negligible. In addition, when noises relating to the data lines, noises due to variations in characteristics of a sense amplifier, and noises of peripheral circuits traveling through a power source circuit are considered, the S/N ratio of the output voltage of the storage cell may be only a few dB.
Therefore, in order to improve the S/N ratio of a read output, the cell array of the TMR-MRAM has been improved as below. A commonly used method is to compare an output voltage V of one selected storage cell to a reference voltage Vref, and differentially amplify a differential voltage Vsig. The purpose of differential amplification is firstly to eliminate noises generated in a data line pair to which the storage cell is connected, and secondly to eliminate the offset of an output voltage due to variations in characteristics of semiconductor devices for sense line drive or for cell selection. However, a circuit generating the reference voltage Vref includes a circuit using a dammy cell or a semiconductor device, and variations in device characteristics between the circuit and the storage cells occur, so it is impossible to completely eliminate the offset of the output voltage in principle.
As a technique for resolving this issue, a method of using a pair of TMR devices to form a storage cell, and differentially amplifying outputs from the pair of TMR devices is widely known. In the method, writing is performed so that the magnetization directions of the magnetic sensitive layers of the pair of TMR devices are always antiparallel to each other. In other words, writing is complementarily performed so that in one of the devices, the magnetization of the magnetic sensitive layer and the magnetization of the pinned layer are parallel to each other, and in the other device, they are antiparallel to each other, and the outputs from the two devices are differentially amplified to read information, thereby common mode noises are eliminated, and the S/N ratio is improved. The structure of such a differential amplification type circuit has been disclosed in Japanese Unexamined Patent Application Publication Nos. 2001-236781 and 2001-266567, ISSCC 2000 Digest paper TA7.2 or the like.
For example, in techniques described in Japanese Unexamined Patent Application Publication Nos. 2001-236781 and 2001-266567, a storage cell includes a first TMR device and a second TMR device, and an end of the first TMR device and an end of the second TMR device are separately connected to a pair of a first data line and a second data line, and the other ends of them are connected to a bit line through a common semiconductor device for cell selection. A word line is connected to the semiconductor device for cell selection. While the first data line and the second data line are maintained at the same potential, a potential difference is applied between the bit line and the first and the second data lines, and the difference value between currents flowing through the first and the second data lines is outputted, thereby information is read out.
However, in such a differential amplification system, in general, variations in resistance between a pair of TMR devices are an issue. The TMR devices have variations in resistance which are produced during a manufacturing process, and a current error due to the variations is inevitable. Therefore, the S/N ratio of an output signal inevitably declines.
Moreover, in the above-described wiring structure example, in order to obtain a stable read signal output, it is necessary to fully prevent variations in resistance between the TMR devices connected to the first line and the second line, and variations in characteristics between semiconductor devices for selection. However, in this case, a voltage difference at the same potential is applied to the first data line and the second data line, so a read current is changed depending upon the above-described variations. In other words, in the structure, the above-described variations cannot be prevented in principle, and there is an issue that it is extremely difficult to take all possible measures against noises due to the variations.
Therefore, in a conventional MRAM, the S/N ratio of the read signal is not sufficiently improved. As a result, although the MR ratio of the device reaches approximately 40%, in an actual TMR-MRAM, a sufficiently large signal output cannot be obtained. Thus, it is assumed that a present memory structure cannot sufficiently respond to a further increase in memory density in addition to having an issue of the structure in operation stability. Moreover, a reduction in power consumption or a reduction in the space of a drive circuit is also an important issue.